The present invention relates in general to semiconductor devices and methods of fabrication, and more particularly to a thin-film transistor structure (TFT) and novel processes for creating the same. The thin-film transistor structure can be used in various integrated circuit devices, such as static random access memories (SRAMs).
Thin-film transistors are field-effect transistors (FETs) that offer major cost and density advantages. However, TFTs have certain undersirable characteristics such as low gain and high off-state leakage current. Unlike a conventional FET where the source, drain and channel regions are formed in the body of a single crystalline substrate, the device regions of a TFT typically are formed in a polysilicon or amorphous silicon layer (device layer) overlying a substrate. Since the polysilicon layer is formed at a relatively lower temperature, and need not be in the body of the single crystal substrate, the device regions of the TFT can be formed above the substrate to create stacked transistors, which is an advantage that provides greater density and lower costs. TFTs are often used in flat panel displays as switching transistors and in static random access memories (SRAMs) as load devices.
Since the device polysilicon layer (channel layer) is conventionally not part of the substrate, a gate insulator and electrode can be positioned over the channel layer (top-gate TFT), or under the channel layer (bottom-gate TFT). Whereas both top-gated and bottom-gated TFTs have been used in SRAMs, bottom-gated TFTs are more popular since they lead to greater packing density. Unfortunately, the conventional bottom-gated TFT suffers certain disadvantages by requiring (1) an extra mask since source and drain regions are defined by topography masking techniques, and (2) drain off-sets that are lithographically defined and hence not self-aligned and symmetrical. These fabrication requirements cause inconsistent xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d currents. Drain off-sets are a desired feature in TFTs and are simply lightly doped regions placed outside the edge of the gate conductor, somewhat similar to lightly doped drain (LDD) FETs. Drain off-sets reduce punch-through problems and reduce the off-state leakage current.
TFT structures are described in various references in the art. For example, reference U.S. Pat. No. 5,573,964, which is hereby incorporated herein by reference in its entirety. This commonly-assigned patent describes a method of making a thin-film transistor (TFT) on a substrate with an insulating surface layer. A layer of dopant source is deposited on the insulating layer, followed by the defining of a gate stack comprising a gate polysilicon, gate insulator and a protective polysilicon using the dopant source layer as an etch stop. Sidewall spacers are formed in contact with the gate stack. A TFT body polysilicon is deposited and patterned, forming thereby the source and drain regions in a self-aligned manner. By heating, the dopants from the dopant source layer are driven into the source/drain and to part of the off-set regions of the body polysilicon layer while simultaneously also doping the gate polysilicon. Although providing an improved manufacturing process for a TFT with improved yield and reliability, as well as employing a self-aligned process for forming the source and drain regions of the TFT, further TFT structure and manufacturing enhancements over this approach are still believed commercially desirable.
High density SRAM memory structures comprising pull-up load transistors (e.g. PMOS), made by thin-film transistors (TFT) lying on top of pull-down devices (e.g. NMOS), typically have a non-planar surface. For example, the top surface of the gate is typically higher than the gate surface of the support devices. Extra processes must then be performed to planarize such a topography so that high quality metal interconnect can be realized to achieve high-density integration. By way of example, the above-referenced U.S. Pat. No. 5,573,964 describes TFT devices formed on top of a gate structure. The gate structure comprises a doped substrate and doped sidewall spacers. The source/drain of the TFT is formed by dopants out-diffusing from these doped substrate and sidewalls. As a result, the source/drain of the TFT device is self-aligned to the gate. Unfortunately, the non-planar topology still means low yield. Also, since the TFT is butted to the underlying active device, separation of the two devices is difficult.
Damascene gate processing has become more and more popular, especially for forming deep-sub-micron devices with a planar surface. One unique aspect of the damascene gate process is that the source/drain of the device is formed first using a dummy gate structure. The gate dielectric and gate conductors are formed afterward. As a result, the gate dielectric is subjected to less thermal cycling. Conventional polysilicon gate semiconductors can be replaced with a low-resistive metal, with a melting point which may be lower than the doped polysilicon. Also, when the dummy gate is removed, a channel implant can be conducted in a self-aligned manner so as to reduce the parasitic capacitance. After the gate is formed, a planar topology is obtained by a chemical-mechanical polish, thereby readying the structure for the following metal interconnect layers.
In view of the above, presented herein is a transistor fabrication approach which employs a dual damascene process to form, in one embodiment, a high-density SRAM memory cell. As one example, the cell may comprise thin-film pull-up devices, NMOS pull-down devices and transfer devices. In addition, a fabrication approach is presented which integrates the process steps for forming SRAM cell devices, and the support devices, wherein the support devices are formed by a single damascene process and the SRAM memory cell devices are formed by a standard damascene or dual damascene process. That is, the TFT devices are formed on top of the pull-down devices and share the same gate conductors. In another aspect, the thin-film transistors presented herein provide a planar surface immediately after the devices are fabricated, where the planar surface is ready for metal interconnect without additional chemical mechanical polishing. In the embodiments described, an upper surface of the TFT gate is coplanar to the gate of the support devices, and the upper surface of the source region, body region and drain region are all coplanar. (Note that the support devices can comprise NMOS and PMOS devices for support circuits, such as decoders, sense amplifiers, word-line drivers, etc. The support devices are typically outside of the memory arrays.) Presented herein is a novel SRAM memory cell structure in which the TFT gate is formed on top of the pull-down NMOS device with a self-aligned source/drain doping from the surrounding doped dielectric material.
The above-summarized objects and advantages are realized herein in one aspect through the provision of a semiconductor device which includes a first field-effect transistor and a second field-effect transistor. The first field-effect transistor has a first source, a first drain and a gate, while the second field-effect transistor has a second source, a second drain and a gate, wherein the gate is shared by the first transistor and the second transistor. In addition, the second source and the second drain are self-aligned to the gate in a layer of planarized semiconductor above the first field-effect transistor.
In another aspect, presented herein is a semiconductor device which includes a first field-effect transistor and a second field-effect transistor. The first field-effect transistor has a first source, a first drain and a gate. The second field-effect transistor has a second source, a second drain and a gate, where the gate is shared by the first transistor and the second transistor. Further, the gate comprises a U-shaped, wrap-around gate for the second field-effect transistor.
In still another aspect, a semiconductor device is presented which includes a masking structure and a semiconductor material layer disposed over the masking structure. The device further includes a doped dielectric layer adjacent to the semiconductor material. The semiconductor material is doped self-aligned to the masking structure from the doped dielectric layer. In a PMOS thin-film transistor (TFT) embodiment, the dielectric material is heavily doped with p type dopants.
Various methods of fabricating the above-summarized semiconductor devices are also described and claimed herein.
Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.